The present invention generally relates to configuring programmable logic devices and testing designs implemented thereon, and more particularly to interactively implementing and testing logic cores on a programmable logic device.
Logic cores are generally used as building blocks in creating electronic circuit designs. A logic core typically is a design that when implemented in hardware performs a predetermined function and that has input and output signal lines that can be connected to other logic. For example, one particular logic core may implement a digital filter, and another logic core may implement a constant multiplier.
The traditional tools for creating logic cores generally support design entry via schematics or a hardware description language such as HDL or VHDL. In addition, there are a multitude of proprietary languages for creating logic cores that are specifically suitable for a particular family of devices. Some environments, for example VHDL, support creation of test environments along with the designs themselves.
In the context of programmable logic devices, for example, field programmable gate arrays (FPGAs) from Xilinx, there are numerous tools available for testing the functionality of circuits created from logic cores. The tools include functional and physical simulators, BoardScope(trademark) graphical debugger software, and XHWIF hardware interface software.
New developments in the area of creating designs for PLDs are rendering the known test methodologies and tools inadequate. For example, circuit designs, including run-time parameterizable logic cores, can be created in the JBits environment from Xilinx. The JBits environment is a Java-based tool that includes an application programming interface (API) that allows designers to develop logic and write a configuration bitstream directly to a Xilinx FPGA. The JBits API permits the FPGA bitstream to be modified quickly, allowing for fast reconfiguration of the FPGA. With Virtex(trademark) FPGAs, the JBits API can be used to partially or fully reconfigure the internal logic of the hardware device. The JBits environment also supports run-time reconfiguration of FPGAs and also configuration of FPGAs over a communications network, for example, an intranet or the Internet.
The JBits environment can also be used to create a suitable test bench for a circuit design. The drawback, however, is that if during testing it becomes desirable to change the parameterization of a logic core to something other than that which was initially programmed in JBits, the JBits program that implements the logic core must be changed to accommodate the new parameter(s). Changing the JBits program requires both knowledge of the JBits environment and knowledge of how the logic core has been programmed with JBits. This added level of complexity and additional consumption of time may be undesirable from the viewpoint of one testing and debugging the circuit implementation on the FPGA.
A system and method that addresses the aforementioned problems, as well as other related problems, is therefore desirable.
A system and method for developing a circuit design for a programmable logic device are provided in various embodiments. In one embodiment, a tool is provided for interactively modifying a configuration bitstream, downloading the bitstream to a programmable logic device (PLD), and reading back and displaying state information from the PLD. The tool allows a designer to interactively generate a test configuration bitstream, advance the PLD clock, and observe the states of elements in the PLD. The test configuration bitstream can then be interactively modified using the tool and a test sequence repeated.
In one embodiment, the tool is command driven. Responsive to a first command, the tool implements a selected logic core from a library of run-time parameterizable logic cores in a configuration bitstream. The bitstream is downloaded to the PLD. In one embodiment, the bitstream is downloaded in response to the first command, and in another embodiment, the bitstream is downloaded responsive to another command. A second command is available for applying a clock signal to the PLD. After application of the clock signal, states of selected elements implemented by the logic core are reported.
It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims that follow.